1. Field of the Invention
The present invention is related to a circuit to generate different clock frequencies from the processor clock. More particularly, the present invention is directed to a pulse swallower circuit to generate clock signals in the processor to communicate with peripherals and the system bus.
2. Art Background
Processors are being developed which utilize faster and faster clock speeds and therefore achieve a higher performance. Furthermore, some processors include an internal cache which is able to operate at a higher frequency compared to the rest of the system. However, peripherals which couple to the processor are typically not able to operate at as high a clock speed. Therefore, in order to provide a clock signal at a slower speed while maintaining proper timing with the processor, a divide down circuit or pulse swallower circuit is typically implemented to generate a compatible but slower clock signal that is synchronized with the higher speed processor clock.
It is not uncommon that different peripherals have different clock requirements. Some peripherals are able to operate at speeds higher than other peripherals and therefore enable the system to achieve a higher throughput. It is therefore desirable to provide a pulse swallower circuit that is programmable to provide different clock speed outputs to communicate with peripherals having differing clock requirements. Furthermore, different systems may be configured to operate at different frequencies. Therefore, it is desirable to provide a programmable pulse swallower circuit that enables the same processor to be used in systems having varying clock frequencies.